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EL9111, EL9112
Data Sheet May 9, 2007 FN7450.4
Triple Differential Receiver/Equalizer
The EL9111 and EL9112 are triple channel differential receivers and equalizers. They contains three high speed differential receivers with five programmable poles. The outputs of these pole blocks are then summed into an output buffer. The equalization length is set with the voltage on a single pin. Using the Enable pin on the EL9111 and EL9112, the outputs can be placed into a high impedance state enabling multiple devices to be connected in parallel and used in a multiplexing application. The gain can be adjusted up or down on each channel by 6dB using its VGAIN control signal. In addition, a further 6dB of gain can be switched in to provide a matched drive into a cable. The EL9111 and EL9112 have a bandwidth of 150MHz and consume just 108mA on 5V supply. A single input voltage is used to set the compensation levels for the required length of cable. The EL9111 is a special version of the EL9112 that decodes syncs encoded onto the common modes of three pairs of CAT-5 cable by the EL4543. (Refer to the EL4543 datasheet for details.) The EL9111 and EL9112 are available in a 28 Ld QFN package and are specified for operation over the full -40C to +85C temperature range.
Features
* 150MHz -3dB bandwidth * CAT-5 compensation - 50MHz @ 1000 ft - 125MHz @ 500 ft * 108mA supply current * Differential input range 3.2V * Common mode input range -4V to +3.5V * 5V supply * Output to within 1.5V of supplies * Available in 28 Ld QFN package * Pb-free plus anneal available (RoHS compliant)
Applications
* Twisted-pair receiving/equalizer * KVM (Keyboard/Video/Mouse) * VGA over twisted-pair * Security video
Pinouts
EL9111 (28 LD QFN) TOP VIEW
25 SYNCREF 27 ENABLE 27 ENABLE
EL9112 (28 LD QFN) TOP VIEW
24 VCM_G 25 VCM_B 23 VCM_R 22 VSP 21 VINM_B 20 VINP_B 19 VINM_G THERMAL PAD 18 VINP_G 17 VINM_R 16 VINP_R 15 VSM VCTRL 10 VGAIN_R 12 VGAIN_G 13 VGAIN_B 14 VSPO_R 9 VREF 11
23 HOUT
24 VOUT
26 X2
VSMO_B 1 VOUT_B 2 VSPO_B 3 VSPO_G 4 VOUT_G 5 VSMO_G 6 VSMO_R 7 VOUT_R 8 VCTRL 10 VGAIN_R 12 VGAIN_G 13 VGAIN_B 14 VSPO_R 9 VREF 11 THERMAL PAD
22 VSP 21 VINM_B 20 VINP_B 19 VINM_G 18 VINP_G 17 VINM_R 16 VINP_R 15 VSM
VSMO_B 1 VOUT_B 2 VSPO_B 3 VSPO_G 4 VOUT_G 5 VSMO_G 6 VSMO_R 7 VOUT_R 8
EXPOSED DIEPLATE SHOULD BE CONNECTED TO -5V
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
26 X2
28 0V
28 0V
EL9111, EL9112 Ordering Information
PART NUMBER EL9111IL EL9111IL-T7 EL9111IL-T13 EL9111ILZ (Note) EL9111ILZ-T7 (Note) EL9111ILZ-T13 (Note) EL9112IL EL9112IL-T7 EL9112IL-T13 EL9112ILZ (Note) EL9112ILZ-T7 (Note) EL9112ILZ-T13 (Note) PART MARKING 9111IL 9111IL 9111IL 9111ILZ 9111ILZ 9111ILZ 9112IL 9112IL 9112IL 9112ILZ 9112ILZ 9112ILZ TAPE & REEL 7" 13" 7" 13" 7" 13" 7" 13" PACKAGE 28 Ld QFN 28 Ld QFN 28 Ld QFN 28 Ld QFN (Pb-free) 28 Ld QFN (Pb-free) 28 Ld QFN (Pb-free) 28 Ld QFN 28 Ld QFN 28 Ld QFN 28 Ld QFN (Pb-free) 28 Ld QFN (Pb-free) 28 Ld QFN (Pb-free) PKG. DWG. # L28.4x5A L28.4x5A L28.4x5A L28.4x5A L28.4x5A L28.4x5A L28.4x5A L28.4x5A L28.4x5A L28.4x5A L28.4x5A L28.4x5A
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN7450.4 May 9, 2007
EL9111, EL9112
Absolute Maximum Ratings (TA = +25C)
Supply Voltage between VS+ and VS- . . . . . . . . . . . . . . . . . . . . .12V Maximum Continuous Output Current per Channel. . . . . . . . . 30mA Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Pin Voltages . . . . . . . . . . . . . . . . . . . . . . . . . VS- -0.5V to VS+ +0.5V
Thermal Information
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Die Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . +150C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER AC PERFORMANCE BW SR THD Bandwidth Slew Rate
VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25C, exposed die plate = -5V, unless otherwise specified. CONDITIONS MIN TYP MAX UNIT
DESCRIPTION
(See Figure 1) VIN = -1V to +1V, VG = 0.39, VC = 0, RL = 75 + 75 10MHz 2VP-P out, VG = 1V, X2 gain, VC = 0
150 1.5 -50
MHz kV/s dBc
Total Harmonic Distortion
DC PERFORMANCE V(VOUT)OS VOS Offset Voltage Channel-to-Channel Offset Matching X2 = high, no equalization X2 = high, no equalization -110 -100 -10 0 +78 +100 mV mV
INPUT CHARACTERISTICS CMIR ONOISE Common-mode Input Range Output Noise VG = 0V, VC = 0V, X2 = HIGH, RLOAD = 150, Input 50 to GND, 10MHz Measured at 10kHz Measured at 10MHz 10k||10pF load Measured @ +1V to -1V Capacitance VINP to VINM Resistance VINP to VINM Capacitance VINP = VINM to GND Resistance VINP = VINM to GND DCBIAS @ VINP = VINM = 0V DCBIAS @ VINP = VINM = 0V VINP - VINM when slope gain falls to 0.9 2.5 1 1 -4 to +3.5 -110 V dBm
CMRR CMRR CMBW CMSLEW CINDIFF RINDIFF CINCM RINCM +IIN -IIN VINDIFF
Common-mode Rejection Ratio Common-mode Rejection Ratio CM Amplifier Bandwidth CM Slew Rate Differential Input Capacitance Differential Input Resistance CM Input Capacitance CM Input Resistance Positive Input Current Negative Input Current Differential Input Range
-80 -55 50 100 600 2.4 1.2 2.8 1 1 3.2
dB dB MHz V/s fF M pF M A A V
OUTPUT CHARACTERISTICS V(VOUT) I(VOUT) R(VCM) Gain Output Voltage Swing Output Drive Current CM Output Resistance of VCM_R/G/B (EL9112 only) Gain RL = 150 RL = 10, VINP = 1V, VINM = 0V, X2 = high, VG = 0.39 at 100kHz VC = 0, VG = 0.39, X2 = 5, RL = 150 0.85 50 3.5 60 30 1.0 1.1 V mA
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FN7450.4 May 9, 2007
EL9111, EL9112
Electrical Specifications
PARAMETER Gain @ DC Gain @ 15MHz V(SYNC)HI V(SYNC)LO SUPPLY ISON ISOFF PSRR Supply Current per Channel Supply Current per Channel Power Supply Rejection Ratio VENBL = 5, VINM = 0 VENBL = 0, VINM = 0 DC to 100kHz, 5V supply 32 0.2 65 36 39 0.4 mA mA dB VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25C, exposed die plate = -5V, unless otherwise specified. CONDITIONS VC = 0, VG = 0.39, X2 = 5, RL = 150 VC = 0.6, VG = 0.39, X2 = 5, RL = 150, Frequency = 15MHz V(VSP) - 0.1V 0 MIN TYP 3 3 MAX 6 10 V(VSP) VSYNCREF + 0.1V UNIT % %
DESCRIPTION Channel-to-Channel Gain Matching Channel-to-Channel Gain Matching High Level output on V/HOUT (EL9111 only) Low Level output on V/HOUT (EL9111 only)
LOGIC CONTROL PINS (ENABLE, X2) VHI VLOW ILOGICH ILOGICL Logic High Level Logic Low Level Logic High Input Current Logic Low Input Current VIN - VLOGIC ref for guaranteed high level VIN - VLOGIC ref for guaranteed low level VIN = 5V, VLOGIC = 0V VIN = 0V, VLOGIC = 0V 1.35 0.8 50 15 V V A A
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 EL9111IL PIN NAME VSMO_B VOUT_B VSPO_B VSPO_G VOUT_G VSMO_G VSMO_R VOUT_R VSPO_R VCTRL VREF VGAIN_R VGAIN_G VGAIN_B VSM VINP_R VINM_R VINP_G VINM_G VINP_B EL9111IL PIN FUNCTION -5V to blue output buffer Blue output voltage referenced to 0V pin +5V to blue output buffer +5V to green output buffer Green output voltage referenced to 0V pin -5V to green output buffer -5V to red output buffer Red output voltage referenced to 0V pin +5V to red output buffer Equalization control voltage (0V to 1V) Reference voltage for logic signals, VCTRL and VGAIN pins Red channel gain voltage (0V to 1V) Green channel gain voltage (0V to 1V) Blue channel gain voltage (0V to 1V) -5V to core of chip Red positive differential input Red negative differential input Green positive differential input Green negative differential input Blue positive differential input EL9112IL PIN NAME VSMO_B VOUT_B VSPO_B VSPO_G VOUT_G VSMO_G VSMO_R VOUT_R VSPO_R VCTRL VREF VGAIN_R VGAIN_G VGAIN_B VSM VINP_R VINM_R VINP_G VINM_G VINP_B EL9112IL PIN FUNCTION -5V to blue output buffer Blue output voltage referenced to 0V pin +5V to blue output buffer +5V to green output buffer Green output voltage referenced to 0V pin -5V to green output buffer -5V to red output buffer Red output voltage referenced to 0V pin +5V to red output buffer Equalization control voltage (0V to 1V) Reference voltage for logic signals, VCTRL and VGAIN pins Red channel gain voltage (0V to 1V) Green channel gain voltage (0V to 1V) Blue channel gain voltage (0V to 1V) -5V to core of chip Red positive differential input Red negative differential input Green positive differential input Green negative differential input Blue positive differential input
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FN7450.4 May 9, 2007
EL9111, EL9112 Pin Descriptions
PIN NUMBER 21 22 23 24 25 26 27 28 EL9111IL PIN NAME VINM_B VSP HOUT VOUT SYNCREF X2 ENABLE 0V Thermal Pad (Continued) EL9111IL PIN FUNCTION Blue negative differential input +5V to core of chip Decoded Horizontal sync referenced to SYNCREF Decoded Vertical sync referenced to SYNCREF Reference level for HOUT and VOUT logic outputs Logic signal for x1/x2 output gain setting Chip enable logic signal 0V reference for output voltage Must be connected to -5V EL9112IL PIN NAME VINM_B VSP VCM_R VCM_G VCM_B X2 ENABLE 0V EL9112IL PIN FUNCTION Blue negative differential input +5V to core of chip Red common-mode voltage at inputs Green common-mode voltage at inputs Blue common-mode voltage at inputs Logic signal for x1/x2 output gain setting Chip enable logic signal 0V reference for output voltage
Typical Performance Curves
5 X2=LOW VGAIN=0V VCTRL=0V RLOAD=150
3 GAIN (dB)
1
-1
-3
-5 1M
10M FREQUENCY (Hz)
100M 200M
FIGURE 1. FREQUENCY RESPONSE OF ALL CHANNELS
FIGURE 2. GAIN vs FREQUENCY ALL CHANNELS
FIGURE 3. GAIN vs FREQUENCY FOR VARIOUS VCTRL
FIGURE 4. GAIN vs FREQUENCY FOR VARIOUS VCTRL AND VGAIN
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FN7450.4 May 9, 2007
EL9111, EL9112 Typical Performance Curves (Continued)
FIGURE 5. GAIN vs FREQUENCY FOR VARIOUS VCTRL AND CABLE LENGTHS
FIGURE 6. CHANNEL MISMATCH
FIGURE 7. GROUP DELAY vs FREQUENCY FOR VARIOUS VCTRL
FIGURE 8. OUTPUT NOISE
FIGURE 9. OFFSET vs VCTRL
FIGURE 10. DC GAIN vs VGAIN
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FN7450.4 May 9, 2007
EL9111, EL9112 Typical Performance Curves (Continued)
-10 VGAIN=0.35V (ALL CHANNELS) -20 VCTRL=0V X2=HIGH CMRR (dB) -40 GAIN (dB) 1M 10M 100M 4 VGAIN=0.35V (ALL CHANNELS) 2 VCTRL=0V RLOAD=150 X2=HIGH 0
-60
-2
-80
-4
-100 100K
-6 100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 11. COMMON-MODE REJECTION
FIGURE 12. CM AMPLIFIER BANDWIDTH
0 VCC=5V VCTRL=0V -20 VGAIN=0V (ALL CHANNELS) INPUTS ON GND +PSRR (dB) -40 -PSRR (dB) 100 1K 10K 100K 1M 10M 100M
-20 VEE=-5V VCTRL=0V -40 VGAIN=0V (ALL CHANNELS) INPUTS ON GND -60
-60
-80
-80
-100
-100 10
-120 10
100
1K
10K
100K
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 13. (+)PSRR vs FREQUENCY
FIGURE 14. (-)PSRR vs FREQUENCY
FIGURE 15. BLUE CROSSTALK
FIGURE 16. BLUE CROSSTALK
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FN7450.4 May 9, 2007
EL9111, EL9112 Typical Performance Curves (Continued)
FIGURE 17. GREEN CROSSTALK
FIGURE 18. GREEN CROSSTALK
FIGURE 19. RED CROSSTALK
FIGURE 20. RED CROSSTALK
FIGURE 21. RISE TIME AND FALL TIME
FIGURE 22. PULSE RESPONSE FOR VARIOUS CABLE LENGTHS
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FN7450.4 May 9, 2007
EL9111, EL9112 Typical Performance Curves (Continued)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
1.2 POWER DISSIPATION (W) 1 0.8 0.6 0.4 0.2 0
893mW
QF N2
JA =
14
8 0 C/ W
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 23. TOTAL HARMONIC DISTORTION
FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 4.5 4 POWER DISSIPATION (W) 3.5 3.378W 3 2.5 2 1.5 1 0.5 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C)
JA
QF N =3 28 7 C/ W
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7450.4 May 9, 2007
EL9111, EL9112 Applications Information
Logic Control
The EL9112 has two logical input pins, Chip Enable (ENABLE) and Switch Gain (X2). The logic circuits all have a nominal threshold of 1.1V above the potential of the logic reference pin (VREF). In most applications it is expected that this chip will run from a +5V, 0V, -5V supply system with logic being run between 0V and +5V. In this case the logic reference voltage should be tied to the 0V supply. If the logic is referenced to the -5V rail, then the logic reference should be connected to -5V. The logic reference pin sources about 60A and this will rise to about 200A if all inputs are true (positive). The logic inputs all source up to 10A when they are held at the logic reference level. When taken positive, the inputs sink a current dependent on the high level, up to 50A for a high level 5V above the reference level. The logic inputs, if not used, should be tied to the appropriate voltage in order to define their state. cables based on 24awg copper wire (CAT-5 etc.) these parameters vary only a little between cable types, and in general cables exhibit the same frequency dependence of loss. (The lower loss cables can be compared with somewhat longer lengths of their more lossy brothers.) This enables a single equalizing law equation to be built into the EL9112. With a control voltage applied between pins VCTRL and VREF, the frequency dependence of the equalization is shown in Figure 8. The equalization matches the cable loss up to about 100MHz. Above this, system gain is rolled off rapidly to reduce noise bandwidth. The roll-off occurs more rapidly for higher control voltages, thus the system (cable + equalizer) bandwidth reduces as the cable length increases. This is desirable, as noise becomes an increasing issue as the equalization increases.
Contrast
By varying the voltage between pins VGAIN and VREF, the gain of the signal path can be changed in the ratio 4:1. The gain change varies almost linearly with control voltage. For normal operation it is anticipated the X2 mode will be selected and the output load will be back matched. A unity gain to the output load will then be achieved with a gain control voltage of about 0.35V. This allows the gain to be trimmed up or down by 6dB to compensate for any gain/loss errors that affect the contrast of the video signal. Figure 26 shows an example plot of the gain to the load with gain control voltage.
2.0 1.8 1.6 GAIN (V) 1.4 1.2 1.0 0.8 0.6 0.4 0 0.2 0.4 VGAIN 0.6 0.8 1
Control Reference and Signal Reference
Analog control voltages are required to set the equalizer and contrast levels. These signals are voltages in the range 0V 1V, which are referenced to the control reference pin. It is expected that the control reference pin will be tied to 0V and the control voltage will vary from 0V to 1V. It is; however, acceptable to connect the control reference to any potential between -5V and 0V to which the control voltages are referenced. The control voltage pins themselves are high impedance. The control reference pin will source between 0A and 200A depending on the control voltages being applied. The control reference and logic reference effectively remove the need for the 0V rail and operation from 5V (or 0V and 10V) only is possible. However we still need a further reference to define the 0V level of the single ended output signal. The reference for the output signal is provided by the 0V pin. The output stage cannot pull fully up or down to either supply so it is important that the reference is positioned to allow full output swing. The 0V reference should be tied to a 'quiet ground' as any noise on this pin is transferred directly to the output. The 0V pin is a high impedance pin and draws DC bias currents of a few A and similar levels of AC current.
FIGURE 26. VARIATION OF GAIN WITH GAIN CONTROL VOLTAGE
Common Mode Sync Decoding
The EL9111 features common mode decoding to allow horizontal and vertical synchronization information, which has been encoded on the three differential inputs by the EL4543, to be decoded. The entire RGB video signal can therefore be transmitted, along with the associated synchronization information, by using just three twisted pairs.
Equalizing
When transmitting a signal across a twisted pair cable, the high frequency (above 1MHz) information is attenuated more significantly than the information at low frequencies. The attenuation is predominantly due to resistive skin effect losses and has a loss curve which depends on the resistivity of the conductor, surface condition of the wire and the wire diameter. For the range of high performance twisted pair
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FN7450.4 May 9, 2007
EL9111, EL9112
Decoding is based on the EL4543 encoding scheme, as described in Figure 27 and Table 1. The scheme is a threelevel system, which has been designed such that the sum of the common mode voltages results in a fixed average DC level with no AC content. This eliminates the effect of EMI radiation into the common mode signals along the twisted pairs of the cable. The common mode voltages are initially extracted by the EL9111 from the three input pairs. These are then passed to an internal logic decoding block to provide Horizontal and Vertical sync output signals (HOUT and VOUT).
Sync Ref
The Sync Ref pin is the reference level for the logic low of the sync outputs. It can be tied to 0V or -5V, but for typical operation, the Sync Ref pin would tie to 0V. The Sync output logic low level approaches Sync Ref within VCESAT; the logic high will approach VSP within VCESAT. The EL9111 operating with a 10V single supply and Sync Ref at ground will cause the HOUT and VOUT pins to go from ground to VSP, a 10V swing. This is too large a voltage for logic inputs, so an output voltage divider of 1k series from the outputs with 1k to ground will reduce the output logic levels to 0V and 5V. Different logic levels may require different output divider ratios. The Sync Ref is intended to sink all the switching currents as transitions to logic low are made. This prevents switching signals crosstalk to the main chip 0V line, as well as adding the flexibility of referencing to -5V. Thus, the logic output buffer does use Sync Ref as its negative supply. The Sync Ref pin is connected to the analog -5V or analog ground as needed and is a separate pin to prevent noise coupling in the chip.
VOLTAGE (0.5V/DIV)
BLUE CM OUT (CH A) GREEN CM OUT (CH B) RED CM OUT (CH C) VSYNC HSYNC TIME (0.5ms/DIV)
VOLTAGE (2.5V/DIV)
EL9111 with Single Ended Coax Input
The EL9111 is designed to use twisted pair cat 5 cable input with sync encoded as differential CMV on the RGB pairs. Coax cable inputs may be used with a few changes and limitations. Coax cable cannot have sync encoded as CMV, so the coax shields are grounded along with the EL9111 RGB minus inputs. The coax center conductor is terminated with 75 and connected to the RGB plus inputs. The result is half the video signal will be seen as CMV by the sync decoding circuit that decodes the video as sync. This causes noise on the RGB outputs. The noise may be eliminated by connecting the Sync Ref pin to VSP to disable the Sync Outputs which now typically go to about 3V with +5VSP.
FIGURE 27. H AND V SYNCS ENCODED TABLE 1. H AND V SYNC DECODING RED CM Mid High Low Mid GREEN CM High Low High Low BLUE CM Low Mid Mid High HSYNC Low Low High High VSYNC Low High Low High
NOTE: Level `Mid' is halfway between `High' and `Low'
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FN7450.4 May 9, 2007
EL9111, EL9112
Power Dissipation
The EL9111 and EL9112 are designed to operate with 5V supply voltages. The supply currents are tested in production and guaranteed to be less than 39mA per channel. Operating at 5V power supply, the total power dissipation in Equation 1 is:
V OUTMAX PDMAX = 3 x 2 x V S x I SMAX + ( V S - V OUTMAX ) x --------------------------RL (EQ. 1)
where: * PDMAX = Maximum power dissipation * VS = Supply voltage = 5V * IMAX = Maximum quiescent supply current per channel = 39mA * VOUTMAX = Maximum output voltage swing of the application = 2V RL = Load resistance = 150
PD MAX = 1.29W (EQ. 2)
JA required for long term reliable operation can be calculated. This is done using the equation:
TJ - TA JA = ------------------- = +50.4C/W PD (EQ. 3)
where: TJ is the maximum junction temperature (+150C) TA is the maximum ambient temperature (+85C) For a QFN 20 Ld package in a properly layout PCB heatsinking copper area, +37C/W JA thermal resistance can be achieved. To disperse the heat, the bottom heatspreader must be soldered to the PCB. Heat flows through the heatspreader to the circuit board copper then spreads and converts to air. Thus the PCB copper plane becomes the heatsink. This has proven to be a very effective technique. "See Technical Bulletin 389 (http://www.intersil.com/data/tb/TB389.pdf) for additional QFN PCB layout information."
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 12
FN7450.4 May 9, 2007
EL9111, EL9112
Package Outline Drawing
L28.4x5A
28 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 10/06
PIN 1 INDEX AREA 4.00 A 2.65 B 0.40 23 22 28 1 PIN #1 INDEX AREA CHAMFER 0.400 X 45
0.5x7=3.50 REF 0.10 C
5.00
3.65
0.50
0.10 2X
15 14 0.50 9
8
0.25 0.5x5=2.50 REF 3.20 REF BOTTOM VIEW
0.10 M C A B
TOP VIEW
MAX. 1.00 PACKAGE BOUNDARY
SEE DETAIL ''X''
(0.40)
C SEATING PLANE 0.08 C SIDE VIEW (28X 0.25)
0.00-0.05
(4.200)
(3.65)
(0.50)
C
0.20REF
5
0~0.05 (28X 0.60) (2.65) (3.20) TYPICAL RECOMMENDED LAND PATTERN DETAIL "X"
NOTES: 1. Controlling dimensions are in mm.
Dimensions in ( ) for reference only.
2. Unless otherwise specified, tolerance : Decimal 0.05
Angular 2
3. Dimensioning and tolerancing conform to AMSE Y14.5M-1994.
4. Bottom side Pin#1 ID is diepad chamfer as shown. 5. Tiebar shown (if present) is a non-functional feature.
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4.20
FN7450.4 May 9, 2007

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